Semiconductor devices are used in many electronic applications, such as radios, televisions, cell phones and computers, as examples. Semiconductor devices are often fabricated as integrated circuits, with hundreds or thousands devices often being manufactured on a single chip.
Semiconductor devices are typically manufactured by depositing several insulating, conducting, and semiconductor layers over a workpiece, and patterning each layer to form conductive lines and electrical circuit elements therein. Metallization layers are usually used for the interconnect layers of semiconductor devices. In multi-level metallization schemes, these metallization layers have insulating layers or inter-level dielectric layers (ILD) disposed between each metallization layer, with vias formed within the ILD layer that provide vertical electrical connection for the semiconductor device.
For many years, aluminum was the preferred choice of material for interconnect layers of semiconductor devices. Aluminum is advantageous in that it may be patterned in a subtractive etch process, e.g., a layer of aluminum is deposited, photoresist is deposited over the aluminum layer, the photoresist is patterned, and then the photoresist is used as a mask while exposed portions of the aluminum are removed in a subtractive etch process.
However, to improve device function and efficiency, copper is being used more and more as a material for interconnections because of its low resistivity, high melting point, and superior electromigration endurance. Copper is also advantageous as an interconnect material because of its stress-void resistance improvement over aluminum. However, copper is difficult to etch in a subtractive process; therefore, copper is usually patterned using damascene processes.
FIG. 1 illustrates a cross-sectional view of a semiconductor device 100 in which conductive lines will be formed in a damascene process, and will be described herein in accordance with a prior art process. A workpiece 110 which may comprise a silicon substrate, for example, is provided. An insulating layer 112 is deposited or formed over the workpiece 110. The insulating layer 112 is patterned, for example, using traditional photolithography techniques and a photoresist. The pattern formed in the insulating layer 112 comprises the pattern for conductive lines that will be formed. A liner 114 may be deposited over the insulating layer 112, particularly if the conductive lines comprise copper, for example. A conductive material 116, which may comprise copper, for example, is deposited over the liner 114, as shown. The conductive material 116 has a top surface that is relatively conformal to the underlying topography of the insulating layer 1112. For example, the conductive material 116 may have a recess formed over the top of the trench in the insulating layer 112 for the conductive lines.
To form conductive lines in the insulating layer 112, the insulating layer 112 is planarized, for example, using a chemical-mechanical polish (CMP) process to remove the conductive material 116 and the liner 114 from the top surface of the insulating layer 112, as shown in FIG. 2. A disadvantage of using a CMP process to remove excess conductive material 116 and liner 114 from the top surface of the insulating layer 112 is that the copper material 116 dishes or forms a recess 118 below the top surface of the insulating layer 112, as shown. The erosion, recess or dishing 118 is undesirable because the conducting area of the conductive material 116 is reduced and the sheet resistance of the conductive material 116 is increased.
What is needed in the art is a method of forming copper damascene conductive lines that has reduced dishing and/or no dishing at all of the copper conductive lines.